1. Field of the Invention
The present invention relates to an improved data processing system employing digital techniques and more particularly to an improved memory refreshing system included therein.
2. Description of Prior Art
In the prior art, various problems existed with regard to parallel transmission of digital information (all data bits transferring simultaneously) between the data processor's CPU and various peripheral devices. These problems related to the relatively large number of wires required in the connecting bus for the parallel transmission scheme. These many parallel paths, in turn, required a like number of drivers and receivers for each peripheral device TELETYPE printer, CRT display, etc.) connected thereto. The complexity of this input/output system reduced the reliability and increased the cost of the overall data processor system.
Parallel transmission, and the resulting large number of connecting wires, was employed in the prior art because the CPU was required to perform many functions, such as instruction decoding. Decoding results in parallel data paths. In order to reduce this large number of wires with their inherent problems, a prior art solution transferred many functions performed by the CPU to the jurisdiction of peripheral device controllers. Accordingly, a parallel to serial data conversion was made in the CPU, a serial transmission of data employed, and a serial to parallel reconversion of data made in the controllers. Since serial transmission of data (one-by-one) is usually slower than parallel transmission (all data bits transferring at once), a higher clock frequency is needed with serial data transmission to provide reasonable or comparable system speed.
However, this serial-parallel conversion plus high clock rate solution created other prior art problems, which obtained from inherent limitations of bipolar, MOS, and other technology utilized. For example, a well-shaped pulse (clock, data, or command) can become a distorted signal at the end of a transmission line or bus cable, depending upon length of the line, quality of the line, frequency of transmission, external noise, and other factors. Use of a higher transmission frequency for serial transmission of data to maintain good system speed facilitates the deterioration of pulses transmitted. The sampling of this kind of distorted signal to re-create a workable pulse is a further problem of the prior art, even when employing state-of-the-art MOS technology. Furthermore, skewing (or phase-shifting) of data caused by inherent limitations of bipolar technology when operating upon a serial data stream is a prior art concern.
As noted, in the prior art, delegation of more control functions from the CPU to other subsystems have been made. There have been developed peripheral device controller (IOC) subsystems which have their own control store for carrying out their required control functions. Similarly, peripheral processors are now being designed with their own control store units. While each control apparatus provides means for controlling the manipulation of its own processor, it also may possibly provide means for controlling manipulations which occur within other processors. But, this combination of multiple control apparatus and processing units presents synchronization of operations and pulse propagation delay problems; accordingly, the number and displacement along the bus of the peripheral devices of the prior art may have to be restricted for reasons earlier indicated. Examples of patents related to this discussion of input/output digital pulse transmission include U.S. Pat. Nos. 3,931,615; 3,932,841; and 3,934,232.
With regard to MOS memories, static MOS RAMs or ROMs are slower and larger than dynamic memories. Therefore, dynamic memories are more desirable from this point of view; but, dynamic memories suffer from the drawback of inherently losing or dissipating the information stored in the memory. In MOS devices, the storage mechanism is a voltage stored on the inherent capacitance of the MOS device. Capacitance inherently leaks charge, and the memory must therefore be replenished or refreshed within sufficiently short intervals to insure that none of the binary information (data words, instruction words, (etc.) is lost by way of this drawback.
One of the principal problems relating to refreshing of dynamic memories involves delay in the overall system operation because memory must be refreshed within a relatively short period of time. The present invention provides a solution to this problem by integrating the microinstructions which control the refreshing operation into the overall algorithm or flow chart of operating states for the CPU in a sufficient number of strategic places to insure that a memory refresh command will be generated within each and every critical refreshing time interval.